A decoder circuit typically takes an encoded value signal and converts it into a different form. The encoded signal can be more or less efficient in terms of complexity than the decoded signal. An example of encoded signals that are less efficient (meaning more bits to represent a simpler set of binary values) are those used for encryption. An example of a more efficient coding scheme would be binary encoding where a binary value represents the position of a pointer to an array of stored values. Binary value 000 would represent position 0, binary value 100 would represent position 4, etc. There would be 2N positions decoded from an N-bit binary value. There are many types of decoders in the prior art.
The present invention relates to binary decoders such as those used as pointers to an array of memory locations. The present invention also relates to methods for decoding digital values such as addresses. The invention also relates to decoders and methods for decoding used in other applications.
Computer integrated circuit chips (or ICs) commonly have decoders which point to locations or addresses of a memory such as a static random access memory (or SRAM). These address decoders are typically binary encoded and access the entire memory array such that each encoded binary value points to a unique memory location. FIG. 1 shows the architecture of an SRAM 10 having a 3-bit address bus for receiving signals A0 to A2 respectively, which is decoded by a decoder 12 to provide signals on eight pointer or word leads W0 to W7. Each word lead W provides a signal to enable a particular row R0 to R7 of bit cells 14 containing a memory location or which allows that word to be written to or read from depending on additional control logic.
FIG. 2 illustrates prior art 3 to 8 address decoder 12 constructed at the gate level. Address decoder 12 receives address signals A0 to A2 and provides both inverted and non-inverted address signals on lines 16-0 to 16-5, which in turn are provided to a set of AND gates 8-0 to 8-7, which serve as pointer circuits to generate therefrom the signals on pointer leads W0 to W7. FIG. 3 is a truth table that indicates which output word lead W0 to W7 is driven high for each combination of address bits.
Although SRAM 10 receives only three address signals and has eight rows, typical SRAMs receive more than three address signals and have more than eight rows. Therefore, typical SRAMs have a greater length than SRAM 10, and their decoders have a greater length than decoder 12. Since decoder 12 and lines 16 span the entire height of the array, for larger arrays, lines 16 are considerably capacitive. Because lines 16 are driven continuously with new address values, the capacitance of lines 16 is continuously charged and discharged, and the decoder power consumption significantly contributes to the overall power consumed by SRAM 10. For example, when one of intermediate lines 16 is discharged from a high binary voltage to ground by a conventional CMOS circuit, an amount of energy equal to ½ C16V2 is consumed (where C16 is the capacitance of that line and V is the voltage on that line prior to being discharged). (The amount of power dissipated is C16V2F, where F is the switching frequency.) One object of this invention is to provide a novel decoder and method that exhibit reduced power consumption.